The current example does not use caches at all, but using instruction cahes does not involve any problems.
Data caches are not possible yet, because no cache coherency mechanism is available.
I don't think cache coherency is the only real trick in doing SMP, there is other tricks like interprocessor communications, interrupt handling, software suppot, and other. It's true that cache coherency is one big trick, and I'm currently working in finding a way to maintain cache coherency in SMP systems that use MicroBlaze.
With this work I want to offer the posibility to try different SMP architectures with the support of an SMP kernel that allows multithreaded applications to run in the different processors in the system.
3 comments:
Hi, so are you using caches or not? The real trick in doing SMP is cache coherency...right?
The current example does not use caches at all, but using instruction cahes does not involve any problems.
Data caches are not possible yet, because no cache coherency mechanism is available.
I don't think cache coherency is the only real trick in doing SMP, there is other tricks like interprocessor communications, interrupt handling, software suppot, and other. It's true that cache coherency is one big trick, and I'm currently working in finding a way to maintain cache coherency in SMP systems that use MicroBlaze.
With this work I want to offer the posibility to try different SMP architectures with the support of an SMP kernel that allows multithreaded applications to run in the different processors in the system.
Regards,
Pablo H
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